1. Field of the Invention
This invention generally relates methods and structures for evaluating and assuring reliability of electronic components. More particularly this invention relates to testing methods and structures to evaluate and minimize burn-in testing of semiconductor wafers onto which integrated circuits are formed.
2. Description of Related Art
As integrated circuit densities and circuit performance has increased, the equipment necessary to evaluate and assure the reliability and functionality of the integrated circuits has become more complex and consequently more expensive. It is well known in the art and shown in FIG. 1 that the hazard rate or probability of failure of integrated circuits follows the commonly referred to xe2x80x9cbathtubxe2x80x9d curve 10. During evaluation of product requirements, the target hazard rate 5 of the integrated circuit is established. Whenever the hazard rate 10 of the integrated circuit exceeds the target hazard rate 5, the integrated circuit is not deemed sufficiently reliable for its intended application. The failures that occur in the early life period 15 of operation of the integrated circuit are referred to as infant mortality.
To predict the actual hazard rate 10 of the integrated circuits, wafer level reliability experiments are performed to detect the failure mechanisms and their impact on the actual hazard rate 10. The predicted hazard rate 20 does not detect lot-to-lot variations that impact the hazard rate 10 nor does it detect and unique variations 25 in the actual hazard rate 10. The reliability experiments facilitate determination of a burn-in schedule that is to eliminate the infant mortality failures from the integrated circuits. However, the lot-to-lot variations may mean that the burn-in schedule may significantly shorten the useful duration 30 of the integrated circuits and in the extreme, cause the integrated circuit to enter the wear-out period 35 earlier than expected.
The reliability evaluation testing and the burn-in testing utilize unique integrated circuit structures to evaluate the results of stress upon the integrated circuit that can cause failure. Typically the structures include, capacitor dielectric film evaluation devices, gate oxide integrity devices, polycrystalline silicon heating devices, contact metallurgy evaluation chains, interlayer via chains, MOS evaluation devices, plasma etching antenna effect patterns, metal electromigration structures, memory cell array, and specially designed circuit block structures. These structures examine the susceptibility of the integrated circuit failures due to such failure mechanisms as pin holes in insulating material such as gate oxides and other inter-level insulating materials, corrosion of metal layers in the presence of moisture, electromigration of the metal layers, etc.
During the technology reliability evaluation the test structures are formed as test sites on an integrated circuit die. An integrated circuit die typically contains one unique test structure to allow creation of a sufficiently large sample size to detect long term or low-level failure phenomena. However, during wafer-level test, the actual functional integrated circuits occupy, as shown in FIG. 2, the die 50 and any test structures or test sites are placed in the kerf or scribe lines 55 area between each integrated circuit die 50. Since the scribe line area 55 is relatively small, the test structure must occupy a relatively small area. This forces a relatively small sample size for evaluation of particular failure mechanisms that have low defect density. Thus, this small sample size does not allow sufficient sensitivity to indicate the defect density prior to burn-in. This forces the burn-in to be longer than necessary to assure that the infant mortality failures are screened from the production lot. For instance, evaluation of the characteristics of individual MOS transistors requires four bonding pads for each device. The bonding pads are relatively large and consume significantly more area than the MOS transistors. Therefore placing test structures for the individual transistors in the scribe lines 55 limits the number of transistors available for evaluation.
U.S. Pat. No. 6,157,046 (Corbett et al.) describes a semiconductor test chip. The semiconductor test chip includes structures for evaluating bond pad design effects and damage (cratering) effects, scribe lane width effects, thermal impedance effects of the die, ion mobility evaluation capabilities, and flip chip on board application test capabilities.
U.S. Pat. No. 6,064,213 (Khandros et al.) describes a wafer-level burn-in and test system that allows a wafer containing integrated circuits to be stressed and evaluated to conduct burn-in of the wafer to assure correct functioning of the wafer.
U.S. Pat. No. 6,246,075 (Su et al.) describes an ensemble of test structures for monitoring gate oxide defect densities and plasma antenna effects. The structures maybe included as a test site on a wafer containing integrated circuits or as test structures for reliability evaluation of an integrated circuit process.
U.S. Pat. No. 5,981,971 (Miyakawa) describes a semiconductor ROM wafer test structure, and IC card. The circuit structure such as the ROM is tested via a test pad formed on a scribe line. Since the test pad is formed on the scribe line, when the die containing the ROM has been cut off and separated from other chips along the scribe lines, the test pads are destroyed preventing future testing of the ROM.
U.S. Pat. No. 5,946,248 (Chien et al.) and U.S. Pat. No. 5,995,428 (Chien et al.) describe methods where a wafer containing memory devices, such as a DRAM (dynamic random access memory) are subjected to a burn-in operation of the memory device. As described in Miyakawa, pads are formed in the scribe lines. These pads are used to transfer an externally generated burn-in enable signal and a DC bias voltage to each memory device. Since the pads for burn-in wiring are formed in the scribe lines, they will not take additional space on the die where each memory device is formed.
U.S. Pat. No. 5,057,441 (Gutt et al.) describes a method for reliability testing integrated circuit metal films using a noise measurement technique. In one embodiment, a film portion to be tested is incorporated in a Wheatstone bridge circuit within a test site. A relatively large direct current is passed through the film to stimulate 1/f2 noise. A relatively small alternating current is concurrently passed through the film. The bridge imbalance signal at the ac frequency is amplified and demodulated by a phase-locked amplifier, and is then frequency analyzed. The film is evaluated by comparing the resulting noise power spectrum with predetermined standards.
U.S. Pat. No. 5,808,947 (McClure) teaches an integrated circuit that includes both a wafer test-mode path that is operable to carry a wafer test-mode signal and a wafer power-supply path that is operable to carry a wafer power-supply signal. The integrated circuit includes functional circuitry that supports normal and wafer-test modes of operation and that is coupled to the wafer test-mode path before the die is detached from the wafer. The functional circuitry is tested for operation when placed in the wafer test mode and functions normally when removed from the wafer test mode. The circuitry for the wafer test-mode path and the wafer power-supply path are located in the scribe line region of the wafer.
U.S. Pat. No. 6,233,184 (Barth et al.) describes structures for wafer level test and burn-in. The structures include a state machine or programmable test engines located on the wafer in the area not including the functional circuitry. Each test engine requires fewer than ten connections and each test engine can be connected to multiple integrated circuit die. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected.
An object of this invention is to provide a method for estimating burn-in time for integrated circuit die on a wafer.
Another object of this invention is to provide a reliability testing structure to permit improved estimation of burn-in time for integrated circuit on a wafer.
Further, another object of this invention is to provide a reliability test structure placed in a scribe line area of a wafer to permit improved estimation of burn-in time for integrated circuits on a wafer.
Still further, another object of this invention is to provide multiple evaluation test devices within a reliability testing structure to permit improved estimation of burn-in time for integrated circuits on a wafer.
To accomplish at least one of these objects and other objects, a method for estimating burn-in time for integrated circuits begins by providing a semiconductor substrate onto which a plurality of reliability testing structures are formed.
Each reliability testing structure has a plurality of evaluation device structures formed on the substrate. Groups of the evaluation device structures are stacked on the surface of the substrate. The device structures are created to permit evaluation of one of a plurality of failure mechanisms of the integrated circuit. The evaluation devices are such devices as capacitor dielectric film evaluation devices, gate oxide integrity devices, polycrystalline silicon heating devices, contact metallurgy evaluation chains, interlayer via chains, MOS evaluation devices, plasma etching antenna effect patterns, metal electromigration structures, memory cell array, and specially designed circuit block structures.
Each evaluation device structure is connected to a first forcing input pad and a first sensing output pad. The first forcing input pad provides a first forcing stimulus to at least one of the evaluation device structures to stress the evaluation device structure. The first sensing output pad is connected to sense a first response signal from at least one of the evaluation device structures.
A second forcing input pad and a second sensing output pad are connected through a selection circuit to at least one of the evaluation devices. The second forcing input pad provides a second forcing stimulus to at least one of the evaluation device structures to further stress the evaluation device structure. The second sensing pad senses a second response signal from the evaluation device structure.
The selection circuit is connected to select which of the evaluation devices are to receive the second stimulus and to transmit the second response. The selection circuit includes a plurality of transmission MOS devices. Each of the transmission MOS devices is connected between the first stimulus input pad and one of the evaluation device structures. A decoder circuit is in communication with a gate terminal of each of the plurality of transmission MOS devices to activate the selected transmission MOS devices to selectively connect at least one of the evaluation device structures to the first stimulus input pad. A counter circuit is in communication with the decoder circuit to create from an increment signal an address code indicating which of the evaluation device structures are to be selected. The increment signal is applied to the decoder through a function control input pad. The increment signal stimulates the counter to increment and, thus, modify the address code to select which of the evaluation device structures are selected.
The counter circuit has an adder circuit, which sums a present address code with the select signal to generate the next address code. The adder circuit communicates with a first transmission gate to selectively transmit the next address code to a first buffer, which receives and retains the next address code. The first buffer is connected to communicate with a second transmission gate, which selectively transmits the next address code from the first buffer to a second buffer, which receives, retains and then transfers the next address code to the decoder. The counter further has a clock modulator that receives the select signal and provides first and second select signals to selectively activate the first and second transmission gates to transfer the next address code to the first and second buffers.
A first delaying circuit is optionally placed between the adder circuit and the first transmission gate to adjust timing of the transmitting of the next address code from the adder circuit to the first transmission gate. A second delaying circuit is placed between the first transmission gate and the first buffer to adjust timing of the transmitting of the next address code from the first transmission gate to the first buffer. A third delaying circuit is placed between the first buffer and the second transmission gate to adjust timing of the transmitting of the next address code from the first buffer to the second transmission gate. And, a fourth delaying circuit is placed between the second transmission gate and the second buffer to adjust timing of the transmitting of the next address code from the second transmission to the second buffer.
The counter further has an initial value circuit that places an initial value at the input of the second transmission gate. This establishes an initial value for the next address code and therefore sets a beginning count for the counter.
The adder has a first summing circuit that is to receive and add the increment signal and a least significant bit of the present address code to form a least significant bit of the next address code. A first carry circuit is connected to receive the increment signal and the least significant bit of the present address code to determine a first carry bit from the sum of the increment signal and the least significant bit of the present address code. The adder has plurality of summing circuits, where each summing circuit is connected to receive and add one of plurality of bits of the present address code and a carry bit. The carry bit is determined from an adjacent less significant bit of the present address code to form one of a plurality of bits of the next address code. Each of a plurality carry circuits is connected to also receive one of the plurality of bits of the present address code and the carry bit determined from the adjacent less significant bit of the present address code to form one of a plurality of carry bits.
Each of the summing circuits is an exclusive-OR gate. The exclusive-OR gate has a MOS transistor of a first conductivity type and a MOS transistor of a second conductivity type. The gates of the MOS transistors are connected to a first input terminal and drains are connected to a second input terminal. First and second inverter circuits are connected such that an input of the first inverter circuit and the output of the second inverter circuit are connected to a source of the MOS transistor of the first conductivity type and an output of the first inverter circuit and the input of the second inverter circuit are connected to a source of the MOS transistor of the second conductivity type. The first and second inverter circuits are standard CMOS inverter circuits thus the exclusive-OR circuit is formed of six transistors. The output terminal of the exclusive-OR circuit is formed at the connection of the source of the MOS transistor of the first conductivity type, the output of the first inverter circuit, and the input of the first inverter circuit.
The carry circuit is an AND circuit having a first MOS transistor of the first conductivity type. The gate of the first MOS transistor of the first conductivity type is connected to a first input terminal, the source is connected to an output terminal, and the drain is connected to a voltage reference terminal. The AND circuit has second MOS transistor of the second conductivity type with a gate connected to a second input terminal, a source connected to the output terminal, and a drain connected to a voltage reference terminal. To complete the AND circuit, a first depletion MOS transistor of the second conductivity type has its gate and source connected to the output terminal and a drain connected to a voltage supply terminal.
The clock modulator circuit has a resistor capacitor network connected to receive the increment signal and to slow the transitions of the increment signal so as to adjust a time at which the increment signal is at an active voltage level. A first buffering circuit is connected to the resistor capacitor network to generate a first select signal from the increment signal with the slowed transitions and a second buffering circuit is connected to the resistor capacitor network to generate a second select signal from the increment signal with slowed transitions. The first and second select signals are generally out of phase from each other.
A resistor, a capacitor and a depletion MOS transistor of the first conductivity type form the initial value circuit. The resistor has a first terminal connected to a voltage supply terminal. The capacitor has a first terminal connected to the second terminal of the resistor and a second terminal connected to a voltage reference terminal. The gate of the second depletion MOS transistor of the first conductivity type is connected to the connection of the first terminal of the capacitor and the second terminal of the resistor. The source is connected to the voltage supply terminal and the drain is connected to an output of the first buffer.
The method continues by selecting which of the testing evaluation devices are to be tested and then activating the first and second stimuli. The substrate is then stressed and each selected evaluation device structure is examined for failure. The hazard rate for each failure mechanism of the integrated circuit is determined and from the hazard rate the burn-in time for the integrated circuit is calculated.